Sabon Asalin XC18V04VQG44C Tabo Hannun Hannun Tabo FPGA Filin Shirye-shiryen Ƙofar Array Logic IC Chip Haɗin Kai.

Halayen Samfur

Takardu & Mai jarida

Rarraba Muhalli & Fitarwa

Ƙarin Albarkatu

Ƙwaƙwalwar Xilinx - Abubuwan Haɓakawa don FPGAs

Xilinx yana gabatar da jerin XC18V00 na cikin-tsarin daidaitawar PROMs (Hoto 1).Na'urorin da ke cikin wannan dangin 3.3V sun haɗa da 4-megabit, 2-megabit, 1-megabit, da kuma 512-kilobit PROM waɗanda ke ba da sauƙi mai sauƙi, hanya mai tsada don sake tsarawa da adanawa lokacinx FPGA sanyi bitstreams.

Lokacin da FPGA ke cikin Yanayin Serial Master, yana haifar da agogo mai daidaitawa wanda ke tafiyar da PROM.Wani ɗan gajeren lokacin shiga bayan an kunna CE da OE, ana samun bayanai akan fil ɗin PROM DATA (D0) wanda ke haɗa da fil ɗin FPGA DIN.Sabbin bayanai suna samun ɗan gajeren lokacin samun dama bayan kowace gefen agogo mai tashi.FPGA yana haifar da adadin adadin agogon da ya dace don kammala daidaitawa.Lokacin da FPGA ke cikin yanayin Serial Slave, PROM da FPGA ana rufe su da agogon waje.

Lokacin da FPGA ke cikin Jagora Zaɓi Yanayin MAP, FPGA yana haifar da agogo mai daidaitawa wanda ke tafiyar da PROM.Lokacin da FPGA ke cikin Slave Parallel ko Slave Select MAP yanayin, wani oscillator na waje yana haifar da agogon sanyi wanda ke tafiyar da PROM da FPGA.Bayan an kunna CE da OE, ana samun bayanai akan fil ɗin DATA (D0-D7).Sabbin bayanai suna samun ɗan gajeren lokacin samun dama bayan kowace gefen agogo mai tashi.An rufe bayanan a cikin FPGA a gefen hawan CCLK mai zuwa.Ana iya amfani da oscillator mai gudana kyauta a cikin Ma'anar Bawa ko Slave Select MAP.

Ana iya jujjuya na'urori da yawa ta amfani da fitowar Shugaba don fitar da shigar da CE na na'urar mai zuwa.Abubuwan shigar da agogo da abubuwan DATA na duk PROMs a cikin wannan sarkar suna da haɗin kai.Duk na'urori sun dace kuma ana iya haɗa su tare da sauran membobin dangi ko tare da dangin PROM masu tsara shirye-shirye na XC17V00 na lokaci ɗaya.