LCMXO2-256HC-4TG100C Asali da Sabo Tare da Farashin Gasa a cikin Mai ba da IC
Halayen Samfur
| Lambar Pbfree | Ee |
| Rohs Code | Ee |
| Sashe na Rayuwa Code Code | Mai aiki |
| Ihs Manufacturer | Abubuwan da aka bayar na LATTICE SEMICONDUCTOR CORP |
| Lambar Kunshin Sashe | QFP |
| Bayanin Kunshin | LFQFP, |
| Ƙididdigar Pin | 100 |
| Isa Lambar Yarda | m |
| ECN Code | EAR99 |
| HTS Code | 8542.39.00.01 |
| Samacsys Manufacturer | Lattice Semiconductor |
| Ƙarin Halaye | Hakanan yana Aiki A 3.3 V NOMINAL SUPPLY |
| JESD-30 Code | Saukewa: S-PQFP-G100 |
| JESD-609 Code | e3 |
| Tsawon | 14 mm |
| Matsayin Ji daɗin Danshi | 3 |
| Adadin abubuwan da aka sadaukar | |
| Adadin Layukan I/O | |
| Adadin abubuwan shigarwa | 55 |
| Adadin abubuwan da aka fitar | 55 |
| Yawan Tasha | 100 |
| Yanayin Aiki-Max | 85 °C |
| Zazzabi Mai Aiki-Min | |
| Ƙungiya | 0 SADAUKAR GABATARWA, 0 I/O |
| Ayyukan fitarwa | GASKIYA |
| Kunshin Jiki Abun | FALASTIC/EPOXY |
| Lambar Kunshin | Farashin LFQFP |
| Lambar Daidaiton Kunshin | TQFP100,.63SQ |
| Siffar Kunshin | SQUARE |
| Salon Kunshin | FLATPACK, KARANCIN PROFILE, KYAUTA |
| Hanyar shiryawa | TRAY |
| Kololuwar Zazzabi (Cel) | 260 |
| Kayayyakin Wutar Lantarki | 2.5 / 3.3 V |
| Nau'in dabaru na shirye-shirye | FLASH PLD |
| Jinkirin Yaduwa | 7,36n ku |
| Matsayin cancanta | Bai cancanta ba |
| Wurin zama Height-Max | 1.6 mm |
| Samar da Voltage-Max | 3.462 V |
| Samar da Voltage-Min | 2.375 V |
| Samar da Voltage-Nom | 2.5 V |
| Dutsen Surface | EE |
| Matsayin Zazzabi | WASU |
| Ƙarshen Tasha | Matte Tin (Sn) |
| Tashar Tasha | GULL WING |
| Filin Tasha | 0.5 mm ku |
| Matsayin Tasha | QUAD |
| Lokaci @ Kololuwar Reflow Temperatuur-Max (s) | 30 |
| Nisa | 14 mm |
Gabatarwar Samfur
Complex Programmable Logic Na'urar (CPLD) wani aikace-aikace ne takamammen Integrated Circuit (ASIC) a cikin LSI (Babban Sikeli Integrated Circuit) Integrated Circuit).Ya dace da tsarin ƙirar tsarin dijital mai ƙarfi mai sarrafawa, kuma sarrafa jinkirin sa ya dace.CPLD yana ɗaya daga cikin na'urori masu girma cikin sauri a cikin haɗaɗɗun da'irori.
Abubuwan da suka dace na CPLD
CPLD hadaddun na'urar dabaru ce mai iya shirye-shirye tare da babban sikeli da hadadden tsari, wanda ke cikin kewayon manyan sikeli.hadedde da'irori.
CPLD yana da manyan sassa guda biyar: toshe tsararru na ma'ana, macro naúrar, tsawaita samfurin lokaci, tsararrun waya mai shirye-shirye da toshewar I/O.
1. Maƙasudin Array Block (LAB)
Toshe ma'ana mai ma'ana ya ƙunshi tsararrun ƙwayoyin macro guda 16, kuma ana haɗa LABS da yawa tare ta hanyar tsararrun tsari (PIA) da bas na duniya.
2. Makiro naúrar
Ƙungiyar macro a cikin jerin MAX7000 ta ƙunshi tubalan aiki guda uku: tsararru mai ma'ana, matrix zaɓin samfur, da rajistar shirye-shirye.
3. Extended samfurin lokaci
Za'a iya mayar da kalma ɗaya samfurin kowane tantanin halitta macro zuwa tsarin ma'ana.
4. PIA mai wayoyi da aka tsara
Ana iya haɗa kowace LAB don samar da dabarun da ake buƙata ta hanyar tsararrun wayoyi.Wannan bas ɗin bas ɗin duniya hanya ce mai tsara shirye-shirye wacce za ta iya haɗa kowane tushen sigina a cikin na'urar zuwa inda za ta.
5. I/O control block
Katangar sarrafa I/O tana ba da damar kowane fil ɗin I/O don daidaitawa daban-daban don shigarwa/fitarwa da aiki bidirectional.
Kwatanta CPLD da FPGA
Ko da yake duka biyuFarashin FPGAkumaFarashin CPLDna'urorin ASIC masu shirye-shirye ne kuma suna da halayen gama gari da yawa, saboda bambance-bambance a cikin tsarin CPLD da FPGA, suna da halayensu:
1.CPLD ya fi dacewa don kammala algorithms daban-daban da haɗin kai, kuma FP GA ya fi dacewa don kammala ma'auni.A takaice dai, FPGA ya fi dacewa da tsarin arziƙi mai jujjuyawa, yayin da CPLD ya fi dacewa da ƙayyadaddun ƙayyadaddun ƙayyadaddun samfur da tsarin wadataccen lokacin samfur.
2.Ci gaba da tsarin tuƙi na CPLD yana ƙayyade cewa jinkirin lokacin sa daidai ne kuma ana iya tsinkaya, yayin da tsarin da aka raba na FPGA ke ƙayyade jinkirin rashin tabbas.
3.FPGA yana da sassauci fiye da CPLD a cikin shirye-shirye.Ana tsara CPLD ta hanyar gyara aikin tunani tare da kafaffen da'irar haɗin ciki, yayin da aka tsara FPGA ta hanyar canza wayoyi na haɗin ciki.Ana iya tsara FP GA a ƙarƙashin ƙofar dabaru, yayin da aka tsara CPLD a ƙarƙashin toshe dabaru.
4.Haɗin FPGA ya fi na CPLD girma, kuma yana da ƙarin tsarin tsarin wayoyi da aiwatar da dabaru.
5.CPLD ya fi dacewa don amfani fiye da FPGA.Shirye-shiryen CPLD ta amfani da fasahar E2PROM ko FASTFLASH, babu guntun ƙwaƙwalwar ajiyar waje, mai sauƙin amfani.Koyaya, bayanan shirye-shirye na FPGA yana buƙatar adanawa cikin ƙwaƙwalwar waje, kuma hanyar amfani tana da rikitarwa.
6. CPLDS sun fi FPgas sauri kuma suna da mafi girman tsinkayar lokaci.Wannan saboda FPGs shirye-shirye ne na matakin kofa kuma ana karɓar haɗin kai tsakanin CLBS, yayin da CPLDS shirye-shirye ne na matakan dabaru da haɗin kai tsakanin tubalan dabaru na su.
7. A cikin tsarin shirye-shirye, CPLD ya dogara ne akan E2PROM ko FLASH memory shirye-shiryen, shirye-shiryen lokutan har zuwa sau 10,000, fa'idar shine cewa tsarin yana kashe bayanan shirye-shirye ba a rasa ba.Ana iya raba CPLD zuwa kashi biyu: shirye-shirye akan mai shirye-shirye da kuma shirye-shirye akan tsarin.Yawancin FPGA suna dogara ne akan shirye-shiryen SRAM, bayanan shirye-shiryen suna ɓacewa lokacin da na'urar ke kashewa, kuma ana buƙatar rubuta bayanan shirye-shiryen zuwa SRAM daga wajen na'urar a duk lokacin da aka kunna ta.Amfaninsa shine ana iya tsara shi kowane lokaci, kuma ana iya tsara shi da sauri a cikin aikin, don cimma daidaito mai ƙarfi a matakin allo da matakin tsarin.
8. Sirrin CPLD yana da kyau, sirrin FPGA mara kyau.
9.In general, da ikon amfani da CPLD ne ya fi girma fiye da na FPGA, da kuma mafi girma da hadewa mataki, mafi bayyananne.
