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XCVU9P-2FLGA2104I - Haɗaɗɗen kewayawa, Haɗe-haɗe, FPGAs (Tsarin Ƙofar Ƙofar Mai Shiryewa)

taƙaitaccen bayanin:

Xilinx® Virtex® UltraScale+™ FPGAs suna samuwa a cikin -3, -2, -1 maki gudun, tare da na'urorin -3E suna da mafi girman aiki.Na'urorin -2LE za su iya aiki a wutar lantarki na VCINT a 0.85V ko 0.72V kuma suna ba da mafi girman matsakaicin ƙarfi.Lokacin da aka yi aiki a VCCINT = 0.85V, ta amfani da na'urorin -2LE, ƙayyadaddun ƙayyadaddun saurin na'urorin L iri ɗaya ne da darajar saurin -2I.Lokacin da aka yi aiki a VCCINT = 0.72V, aikin -2LE da ƙarfi da ƙarfi yana raguwa.An ƙayyade halayen DC da AC a cikin tsawaita (E), masana'antu (I), da na soja (M) kewayon zafin jiki.Sai dai yanayin zafin aiki ko sai in an lura, duk sigogin wutar lantarki na DC da AC iri ɗaya ne don takamaiman matakin saurin gudu (wato, halayen lokaci na na'ura mai tsayin saurin -1 iri ɗaya ne da darajar saurin -1). na'urar masana'antu).Koyaya, makin gudun da aka zaɓa kawai da/ko na'urori suna samuwa a kowane kewayon zafin jiki.


Cikakken Bayani

Tags samfurin

Halayen Samfur

TYPE BAYANI
Kashi Haɗin kai (ICs)

Abun ciki

FPGAs (Field Programmable Gate Array)

Mfr AMD
Jerin Virtex® UltraScale+™
Kunshin Tire
Matsayin samfur Mai aiki
DigiKey Programmable Ba a Tabbatarwa ba
Adadin LABs/CLBs 147780
Adadin Abubuwan Hankali/Cunuka 2586150
Jimlar RAM Bits Farashin 39168000
Adadin I/O 416
Voltage - Samfura 0.825V ~ 0.876V
Nau'in hawa Dutsen Surface
Yanayin Aiki -40°C ~ 100°C (TJ)
Kunshin / Case 2104-BBGA, FCBGA
Kunshin Na'urar Mai bayarwa 2104-FCBGA (47.5x47.5)
Lambar Samfurin Tushen Farashin XCVU9

Takardu & Mai jarida

NAU'IN ARZIKI MAHADI
Takardar bayanai Virtex UltraScale+ FPGA Datasheet
Bayanin Muhalli Xiliinx RoHS Cert

Xilinx REACH211 Cert

Model EDA XCVU9P-2FLGA2104I ta SnapEDA

XCVU9P-2FLGA2104I na Ultra Librarian

Rarraba Muhalli & Fitarwa

SANARWA BAYANI
Matsayin RoHS ROHS3 mai yarda
Matsayin Ji daɗin Danshi (MSL) Awanni 4 (72)
ECN 3A001A7B
HTSUS 8542.39.0001

 

FPGAs

Ka'idar aiki:
FPGAs suna amfani da ra'ayi kamar Logic Cell Array (LCA), wanda a ciki ya ƙunshi sassa uku: Configurable Logic Block (CLB), Block Output Block (IOB) da Interconnect Interconnect.Filin Programmable Gate Arrays (FPGAs) na'urori ne masu shirye-shirye tare da gine-gine daban-daban fiye da da'irar dabaru na gargajiya da tsararrun ƙofa kamar na'urorin PAL, GAL da CPLD.Ana aiwatar da ma'anar FPGA ta hanyar loda ƙwayoyin ƙwaƙwalwar ajiya na ciki tare da bayanan da aka tsara, ƙimar da aka adana a cikin sel ƙwaƙwalwar ajiya sun ƙayyade aikin tunani na sel dabaru da kuma hanyar da aka haɗa samfuran zuwa juna ko zuwa I / O.Ƙimar da aka adana a cikin ƙwayoyin ƙwaƙwalwar ajiya suna ƙayyade aikin ma'ana na sel masu hankali da kuma hanyar da aka haɗa nau'ikan zuwa juna ko zuwa I / Os, kuma a ƙarshe ayyukan da za a iya aiwatarwa a cikin FPGA, wanda ke ba da damar tsara shirye-shirye marasa iyaka. .

Tsarin guntu:
Idan aka kwatanta da sauran nau'ikan ƙirar guntu, mafi girma kofa da ƙarin ƙaƙƙarfan kwararar ƙira yawanci ana buƙata game da guntuwar FPGA.Musamman ma, ƙirar ya kamata a haɗa ta kut da kut da tsarin FPGA, wanda ke ba da damar girman sikelin ƙirar guntu na musamman.Ta amfani da Matlab da algorithms ƙira na musamman a cikin C, ya kamata a sami damar samun sauyi mai sauƙi a duk kwatance kuma don haka tabbatar da cewa ya dace da tunanin ƙirar guntu na yau da kullun.Idan haka ne, to yawanci ya zama dole a mai da hankali kan tsarin haɗin kai na abubuwan haɗin gwiwa da harshen ƙirar da ya dace don tabbatar da ƙirar guntu mai amfani da karantawa.Yin amfani da FPGAs yana ba da damar gyara allon allo, simulation code da sauran ayyukan ƙira masu alaƙa don tabbatar da cewa an rubuta lambar yanzu ta hanya kuma cewa ƙirar ƙirar ta cika ƙayyadaddun buƙatun ƙira.Baya ga wannan, ya kamata a ba da fifikon ƙirar ƙirar ƙira don haɓaka ƙirar aikin da tasirin aikin guntu.A matsayin mai ƙira, mataki na farko shine gina ƙayyadaddun ƙirar algorithm wanda lambar guntu ke da alaƙa.Wannan saboda lambar da aka riga aka tsara tana taimakawa don tabbatar da amincin algorithm kuma yana haɓaka ƙirar guntu gabaɗaya.Tare da cikakken gyaran allo da gwajin kwaikwaiyo, yakamata a rage lokacin sake zagayowar da ake cinyewa wajen zayyana guntu gabaɗaya a tushe kuma don haɓaka tsarin gaba ɗaya na kayan aikin da ke akwai.Ana amfani da wannan sabon ƙirar ƙirar samfuri sau da yawa, misali, lokacin haɓaka mu'amalar kayan masarufi marasa daidaituwa.

Babban ƙalubale a cikin ƙirar FPGA shine sanin tsarin kayan masarufi da albarkatun cikinsa, don tabbatar da cewa yaren ƙira yana ba da damar haɗin kai mai inganci da haɓaka haɓakawa da amfani da shirin.Wannan kuma yana sanya manyan buƙatu akan mai zane, wanda ke buƙatar samun gogewa a cikin ayyukan da yawa don biyan buƙatun.

 Tsarin algorithm yana buƙatar mayar da hankali kan hankali don tabbatar da kammala aikin ƙarshe, don ba da shawarar warware matsalar dangane da ainihin yanayin aikin, da haɓaka ingantaccen aikin FPGA.Bayan kayyade algorithm ya zama m don gina module, don sauƙaƙe ƙirar ƙira daga baya.Ana iya amfani da lambar da aka riga aka ƙera a ƙirar lambar don inganta inganci da aminci.Ba kamar ASICs ba, FPGAs suna da ɗan gajeren zagaye na ci gaba kuma ana iya haɗa su tare da buƙatun ƙira don canza tsarin kayan aikin, wanda zai iya taimaka wa kamfanoni su ƙaddamar da sababbin samfurori da sauri da kuma biyan bukatun ci gaba na rashin daidaituwa lokacin da ka'idojin sadarwa ba su da girma.


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