10AX115H2F34E2SG FPGA Arria® 10 GX Iyali 1150000 Sel 20nm Fasaha 0.9V 1152-Pin FC-FBGA

CPLD shine takaitaccen na'ura mai saurin shirye-shirye, FPGA shine takaitaccen tsari na filin shirye-shiryen ƙofa, aikin biyun ainihin iri ɗaya ne, amma ƙa'idar aiwatarwa ta ɗan bambanta, don haka wani lokaci muna iya watsi da bambanci tsakanin su biyun, tare. ake magana da shi azaman na'urar dabaru ko CPLD/FPGA.Akwai kamfanoni da yawa da ke samar da CPLD/FPGs, manyan ukun su ne ATERA,XILINX, da LAT-TICE.Bazuwar CPLD hada-hadar dabaru aiki yana da ƙarfi sosai, naúrar macro na iya ruɓar dozin ko ma fiye da shigarwar dabaru na 20-30.Koyaya, LUT na FPGA kawai zai iya ɗaukar dabaru na haɗin kai na abubuwan shigarwa guda 4 kawai, don haka CPLD ya dace don ƙirƙira hadadden dabaru na haɗin gwiwa kamar yanke hukunci.Duk da haka, tsarin masana'antu na FPGA yana ƙayyade cewa adadin LUTs da abubuwan da ke kunshe a cikin guntu na FPGA suna da girma sosai, sau da yawa dubban dubban, CPLD na iya cimma kawai 512 raka'a ma'ana, kuma idan an raba farashin guntu da adadin ma'ana. raka'a, matsakaicin farashin naúrar ma'ana na FPGA ya yi ƙasa da na CPLD.Don haka idan an yi amfani da adadi mai yawa na faɗakarwa a cikin ƙira, kamar zayyana madaidaicin lokacin dabaru, to amfani da FPGA zaɓi ne mai kyau.

Ko da yake duka FPGA da CPLD na'urorin ASIC ne masu shirye-shirye kuma suna da halaye na gama-gari, saboda bambance-bambance a cikin tsarin CPLD da FPGA, suna da nasu halayen:

• CPLD ya fi dacewa don kammala algorithms iri-iri da dabaru na haɗakarwa, kuma FPGA ya fi dacewa don kammala dabaru na jeri.A takaice dai, FPGA ya fi dacewa da tsarin arziƙi mai jujjuyawa, yayin da CPLD ya fi dacewa da ƙayyadaddun ƙayyadaddun ƙayyadaddun samfur da tsarin wadataccen lokacin samfur.
• Ci gaba da tsarin tuƙi na CPLD yana ƙayyadad da cewa jinkirin lokacin sa iri ɗaya ne kuma ana iya faɗi, yayin da tsarin FPGA ɗin da aka raba ya ƙayyade cewa jinkirin sa ba shi da tabbas.
• FPGA yana da sassauci fiye da CPLD a cikin shirye-shirye.
• An tsara CPLD ta hanyar gyara aikin tunani na kafaffen da'ira na ciki, yayin da aka tsara FPGA ta hanyar canza wayoyi na haɗin ciki.
• Ana iya tsara Fpgas a ƙarƙashin ƙofofin dabaru, yayin da aka tsara CPLDS a ƙarƙashin tubalan dabaru.
• FPGA ya fi haɗin kai fiye da CPLD kuma yana da ƙarin tsarin tsarin wayoyi da aiwatar da dabaru.

Gabaɗaya, ƙarfin ƙarfin CPLD ya fi na FPGA girma, kuma mafi girman matakin haɗin kai, mafi bayyane.